;================================================================
; ibe.asm - iButton emulator
;
;	(C) 2010 by Tomas Pecina
;
; Device:
; 	ATtiny85
; 
; Fuses:
; 	EFUSE = 0bXXXXXXXX
; 	HFUSE = 0b1XX1X111
;	LFUSE = 0b1X010010
; 	(X = don't care)
	
.nolist
.include "tn85def.inc"
.include "main.inc"
.list

; constants
	.equ	trst = 90
	.equ	tpres = trst + 8
	.equ	trstt = 2 * trst
	.equ	tlow = 1
	.equ	tsmp = 2
	.equ	thigh = 9
	.equ	tslt = 12
	.equ	tc0 = 3
	.equ	tc1 = 80
	.equ	tc2 = 220
	.equ	tc3 = 1
	.equ	tc4 = 78
	.equ	tc5 = 79
	.equ	tc6 = 140
	.equ	tc7 = 3
	.equ	tc8 = 12
	.equ	tc9 = 72
	.equ	tc10 = 5
	.equ	tc11 = 200
	.equ	tc12 = 5
	.equ	tc13 = 250
	.equ	romread = 0x0f
	.equ	romread2 = 0x33
	.equ	sign = 0x01

; pins
	.equ	LED = PB4
	.equ	IBIO = PB3
	.equ	UNUSED1 = PB2
	.equ	EIBI = PB1
	.equ	EIBO = PB0

; blink
	.equ	BLRATE = 35
	.equ	BLRDY = 0b11111
	.equ	BLSLP = 0b1001
	.equ	BLIBI = 0b1100011
	.equ	BLNOE = 0b110001100011

	.dseg
	.org	SRAM_START
ib:
	.byte	8
crc:
	.byte	1

; EEPROM
	.eseg

	.org	0
eibee:
	.byte	8
	
	.cseg

	.org	0
	rjmp	start

	.org	WDTaddr
	rjmp	wdtint

start:
; initialize SP
	ldiw	A, RAMEND
	out	SPH, AH
	out	SPL, AL

; enable WDT
	in	AL, WDTCR
	sbr	AL, (1<<WDCE) | (1<<WDE)
	out	WDTCR, AL
	ldi	AL, (1<<WDIE) | (1<<WDP3) | (1<<WDE) | (1<<WDP0)
	out	WDTCR, AL
	sei

; initialize hardware
	rcall	tmrinit
	ldi	AL, (1<<LED) | (1<<EIBO)	; outputs on LED & EIBO
	out	DDRB, AL
	ldi	AL, (1<<UNUSED1) | (1<<EIBI)	; pull-ups on UNUSED1 & EIBI
	out	PORTB, AL

; sign on
	ldiw	A, BLRDY
	rcall	blink
	
; main loop	
m0:	cbi	PORTB, LED	; LED off
	sbi	PORTB, EIBO	; generate short charging pulse (ca 1us)
	ldi	BL, tc3
m19:	dec	BL
	brne	m19
	cbi	PORTB, EIBO	
	rcall	ibclr		; generate reset pulse while keeping an eye on the emulation port
	rcall	tmrstart
	ldi	AL, trst
	out	OCR0A, AL
	in	AL, TIFR
	sbr	AL, (1<<OCF0A)
	out	TIFR, AL
m2:	in	AL, TIFR
	sbrc	AL, OCF0A
	rjmp	m1
	sbis	PINB, EIBI	; reader polling?
	rjmp	m5
	rjmp	m2
m1:	rcall	ibset		; end of reset pulse
	ldi	AL, tpres
	out	OCR0A, AL
	in	AL, TIFR
	sbr	AL, (1<<OCF0A)
	out	TIFR, AL
m4:	in	AL, TIFR
	sbrc	AL, OCF0A
	rjmp	m3
	sbis	PINB, EIBI	; reader polling?
	rjmp	m5
	rjmp	m4
m3:	rcall	ibread		; presence pulse?
	ldi	AL, trstt
	out	OCR0A, AL
	in	AL, TIFR
	sbr	AL, (1<<OCF0A)
	out	TIFR, AL
m6:	in	AL, TIFR
	sbrc	AL, OCF0A
	rjmp	m7
	sbis	PINB, EIBI	; reader polling?
	rjmp	m5
	rjmp	m6
m7:	brts	m0		; no presence pulse and no reader, repeat until WDT timeout
	wdr			; presence pulse detected, reset WDT
	rcall	crcinit
	ldi	AL, romread
	rcall	ibout		; send command
	ldiw	X, ib
	ldi	BH, 8
m8:	rcall	ibin		; read response
	st	X+, AL
	push	BH
	rcall	crcbyte
	pop	BH
	dec	BH
	brne	m8
	lds	AL, ib
	cpi	AL, sign	; correct iButton type?
	brne	m00
	lds	AL, crc
	tst	AL		; DOW CRC ok?
	brne	m00
	ldiw	A, BLIBI	; indicate good read
	rcall	blink
	ldiw	X, ib		; check if EEPROM write is required
	ldiw	Y, eibee
	ldi	BL, 8
m9:	rcall	readeeprom
	ld	BH, X+
	cp	AL, BH
	brne	m10
	adiw	Y, 1
	dec	BL
	brne	m9
	rjmp	m11		; no, proceed
m10:	ldiw	X, ib		; write to EEPROM
	ldiw	Y, eibee
	ldi	BL, 8
m12:	ld	AL, X+
	rcall	writeeeprom
	adiw	Y, 1
	dec	BL
	brne	m12
m11:	ldi	BH, tc0		; wait until no presence pulse detected for ca 0.5 sec
m14:	clr	BL
m13:	wdr			; reset WDT, presence pulse means device is active
	rcall	ibreset
	brtc	m11
	dec	BL
	brne	m13
	dec	BH
	brne	m14
m00:	rjmp	m0		; iButton removed, return to main loop
m5:	wdr			; reader detected, reset WDT
	rcall	crcinit		; prepare data
	ldiw	Y, eibee
	ldiw	X, ib
	ldi	BL, 8
m22:	rcall	readeeprom
	st	X+, AL
	push	BL
	rcall	crcbyte
	pop	BL
	adiw	Y, 1
	dec	BL
	brne	m22
	lds	AL, ib
	cpi	AL, sign	; correct iButton type?
	brne	m23
	lds	AL, crc
	tst	AL		; DOW CRC ok?
	breq	m24
m23:	ldiw	A, BLNOE
	rcall	blink
	rjmp	m25
m24: 	ldi	BH, tc9		; check if reset pulse
m30:	ldi	BL, tc10
m31:	sbic	PINB, EIBI
	rjmp	m36		; too short, no reset pulse
	dec	BL
	brne	m31
	dec	BH
	brne	m30
m21:	sbis	PINB, EIBI
	rjmp	m21		; wait until reader releases line, no time limitation, but no WDT reset
	ldi	BL, tc1	
m15:	dec	BL
	brne	m15
	sbi	PORTB, EIBO	; emulate presence pulse, pull line
	ldi	BL, tc2
m16:	dec	BL
	rjmp	m17		; dummy jump
m17:	brne	m16
	cbi	PORTB, EIBO	; release line
m18:	sbis	PINB, EIBI
	rjmp	m18		; wait until line released, no WDT reset
	rcall	eibin		; read command
	brts	m24		; no clock pulse received
	cpi	AL, romread
	breq	m20
	cpi	AL, romread2
	breq	m20
	rjmp	m36
m20:	ldiw	X, ib
	ldi	CH, 8
m32:	ld	AL, X+
	rcall	eibout		; write data
	brts	m24		; no clock pulse received
	dec	CH
	brne	m32
	wdr
	sbi	PORTB, LED	; LED on
m36:	ldi	BL, tc12	; check for another pulse within ca 0.2 sec
m35:	clr	BH
m34:	clr	CL
m33:	sbis	PINB, EIBI
	rjmp	m5
	dec	CL
	brne	m33
	dec	BH
	brne	m34
	dec	BL
	brne	m35
	rjmp	m0	
m25:	ldi	BH, tc8		; wait until no activity for ca 0.5 sec
m26:	clr	BL
m28:	clr	CL
m27:	sbis	PINB, EIBI
	rjmp	m25
	dec	CL
	brne	m27
	dec	BL
	brne	m28
	dec	BH
	brne	m26
	rjmp	m0		; done, return to main loop

; generate emulated slot
eibin:
	ldi	AL, 0xff
eibout:
	ldi	CL, 8
	ldi	BH, tc13
e9:	clr	BL
e5:	sbis	PINB, EIBI
	rjmp	e7		; wait for falling edge
	dec	BL
	brne	e5
	dec	BH
	brne	e9
	rjmp	e8
e7:	sbrs	AL, 0
	sbi	PORTB, EIBO	; pull line
	ldi	BL, tc4
e1:	dec	BL
	brne	e1
	ror	AL
	cbr	AL, (1<<7)
	sbic	PINB, EIBI	; sample line
	sbr	AL, (1<<7)
	ldi	BL, tc5
e2:	dec	BL
	brne	e2
	cbi	PORTB, EIBO
	ldi	BH, tc6
e4:	ldi	BL, tc7
e3:	sbis	PINB, EIBI
	rjmp	e6
	dec	CL
	brne	e5
	clt
	ret
e6:	dec	BL
	brne	e3
	dec	BH
	brne	e4
e8:	set
	ret

; WDT interrupt
wdtint:
	cli			; disable interrupts

; disable WDT
	wdr
	in	AL, MCUSR
	cbr	AL, (1<<WDRF)
	out	MCUSR, AL
	in	AL, WDTCR
	sbr	AL, (1<<WDCE) | (1<<WDE)
	out	WDTCR, AL
	cbr	AL, (1<<WDCE) | (1<<WDE)
	out	WDTCR, AL

; blink good-bye
	ldiw	A, BLSLP
	rcall	blink
	
; set pins to powar saving mode
	clr	AL				; all inputs
	out	DDRB, AL
	ldi	AL, (1<<UNUSED1) | (1<<EIBI) 	; pull-ups on UNUSED1 & EIBI
	out	PORTB, AL

; enable sleep & go to power-down sleep
	in	AL, PRR
	sbr	AL, (1<<PRTIM1) | (1<<PRTIM0) | (1<<PRUSI) | (1<<PRADC)
	out	PRR, AL
	in	AL, MCUCR
	andi	AL, (1<<SE) | (1<<SM1) | (1<<SM0)
	ori	AL, (1<<SE) | (1<<SM1)
	out	MCUCR, AL
	sleep

; blink pattern in AX
blink:
b1:	mov	BL, AL
	or	BL, AH
	brne	b4
	cbi	PORTB, LED
	ret
b4:	clc
	ror	AH
	ror	AL
	cbi	PORTB, LED
	brcc	b2
	sbi	PORTB, LED
b2:	push	AL
	ldi	BL, BLRATE
b3:	rcall	tmrstart
	ldi	AL, tc11
	rcall	tmrwait
	dec	BL
	brne	b3
	pop	AL
	rjmp	b1

; initialize timer
tmrinit:
	clr	AL
	out	TCCR0A, AL
	ldi	AL, 3
	out	TCCR0B, AL
	ret

; start timing
tmrstart:
	clr	AL
	out	TCNT0, AL
	ret

; wait until AL * 8us
tmrwait:
	out	OCR0A, AL
	in	AL, TIFR
	sbr	AL, (1<<OCF0A)
	out	TIFR, AL
t1:	in	AL, TIFR
	sbrs	AL, OCF0A
	rjmp	t1
	ret

; initialize IB
ibinit:
	cbi	DDRB, IBIO
	cbi	PORTB, IBIO
	ret

; set IB to LOW
ibclr:
	sbi	DDRB, IBIO
	ret

;  set IB to HIGH
ibset:
	cbi	DDRB, IBIO
	ret

; read IB to T
ibread:
	in	AL, PINB
	bst	AL, IBIO
	ret

; generate reset pulse and check presence pulse (T=no presence pulse)
ibreset:
	rcall	ibclr
	rcall	tmrstart
	ldi	AL, trst
	rcall	tmrwait
	rcall	ibset
	ldi	AL, tpres
	rcall	tmrwait
	rcall	ibread
	ldi	AL, trstt
	rcall	tmrwait
	ret

; generate read/write slot (T=data in/out)
ibslot:
	rcall	tmrstart
	ldi	AL, tlow
	rcall	ibclr
	rcall	tmrwait
	brtc	l2
	rcall	ibset
l2:	ldi	AL, tsmp
	rcall	tmrwait
	rcall	ibread
	ldi	AL, thigh
	rcall	tmrwait
	rcall	ibset
	ldi	AL, tslt
	rcall	tmrwait
	ret

; read/write byte (AL=data in/out)
ibin:
	ldi	AL, 0xff
ibout:
	ldi	BL, 8
l5:	bst	AL, 0
	ror	AL
	push	AL
	rcall	ibslot
	pop	AL
	bld	AL, 7
	dec	BL
	brne	l5
	clt
	ret

; initialize DOW CRC calculation
crcinit:
	clr	AL
	sts	crc, AL
	ret

; calculate next DOW CRC byte (input: AL)
crcbyte:
	lds	CL, crc
	mov	BL, AL
	ldi	BH, 8
l3:	eor	AL, CL
	ror	AL
	mov	AL, CL
	brcc	l4
	ldi	AH, 0x18
	eor	AL, AH
l4:	ror	AL
	mov	CL, r16
	mov	AL, BL
	ror	AL
	mov	BL, AL
	dec	BH
	brne	l3
	mov	AL, BL
	sts	crc, CL
	ret

; read byte from eeprom
readeeprom:
	sbic	EECR, EEPE
	rjmp	readeeprom
	out	EEARH, YH
	out	EEARL, YL
	sbi	EECR, EERE
	in	AL, EEDR
	ret

; write byte to  eeprom
writeeeprom:
	sbic	EECR, EEPE
	rjmp	writeeeprom
	push	AL
	clr	AL
	out	EECR, AL
	pop	AL
	out	EEARH, YH
	out	EEARL, YL
	out	EEDR, AL
	sbi	EECR, EEMPE
	sbi	EECR, EEPE
	ret